1. Field of the Invention
The present invention relates to digital circuits and digital circuit simulation systems and, more particularly, to digital circuits and digital circuit simulation systems which convert a multiple-phase level-sensitive design into a single-clock-edge based system.
2. Description of the Related Art
The design and development of electronic circuits includes the task of building and testing a system prototype. The system prototype may take the form of a breadboard circuit having various degrees of similarity in form and function to the target circuit, a simulated circuit operating on a general purpose computer system, a hardware simulator or emulator and the like. A prototype is generally useful if it is constructed in a suitable time for a reasonable cost, so long as the prototype effectively mimics the function of the target circuit.
The design of highly complex electronic circuits and systems includes an analysis of circuits that contain a large number of active elements. For LSI and VLSI circuits, examination of the total system response involves simulation of hundreds of thousands of circuit elements. Typically simulation of complex circuits is accomplished using a hierarchical approach by analyzing circuits at different levels of abstraction, including simulations at architectural, behavioral, functional, logic and transistor levels. At the architectural level, the abstract definition of the architecture of the circuit is analyzed to set a guideline for the various ways of accomplishing the objective of the circuit. At the behavioral level of simulation, major blocks of the circuit are defined and their interactions are catalogued to examine the details of the overall data or control flow for accomplishing the objective of the circuit. The functional level of simulation describes the overall logical response of the major blocks in the circuit to relate the logical input parameters to output parameters while not considering the details of the internal realization of the logic within the block. The logic level of simulation analyzes each block at the gate level, minimizes logic and in some cases introduces the concept of relative timing. The transistor level simulation examines the transient response of the circuit, including the detailed emulation of all elements within the circuit. Usefulness of the hierarchical simulation is determined by the ability to mix the different levels of abstraction to examine the performance of the entire circuit while analyzing the detailed interactions of circuit elements one block at a time.
Certain simulators, emulators and verification tools update system changes on clock cycle by clock cycle basis. These tools, called cycle-based, edge-triggered, latched or edge-based systems, pass information on the falling or rising edge of a clock signal. These tools accurately reflect the performance of the circuit design by allowing only very simple clocking arrangements, usually a single-clock system which supports edge-triggered flip-flops. In a single clock edge trigger system, all sequential elements are updated during each clock cycle. Latches are inherently transparent so that changes to signals on input lines of a latch are immediately expressed on the latch output lines. A typical single-clock edge triggered system 100, shown in FIG. 1, employs edge-triggered flip-flops 102 and 104 as basic sequential circuit elements which control circuit timing of interspersed combinational logic 106. A single-clock edge triggered system 100 is timed using a simple single phase clocking scheme, which is depicted in FIG. 2. This clocking scheme does not allow clock gating.
An alternative to edge-based designs are level-sensitive designs. A level-sensitive device, also referred to as a transparent device, transfers information while the clock signal is active. A level-sensitive device updates its output information during the relatively long period of time of clock activity in contrast to an edge-triggered device which updates its output information during the small sampling of time that is centered around the edge of the clock signal.
Usage of typical edge-based simulation and emulation tools is advantageous for various reasons. Edge-based tools are simpler and therefore more efficiently perform each operation. Accordingly, edge-based tools emulate larger circuit designs and perform this emulation much more quickly.
Large microprocessors and other complex system designs operate on a multiple-phase clock, resulting in an enhanced performance. In a multi-phase clock system, sequential elements are conditionally updated on selected phases of a clock cycle. A multi-phase clock based system 300, shown in FIG. 3, advantageously uses multiple clock edges generated by out-of-phase clock signals of a single clock cycle to drive combinational logic blocks, for example combinational logic blocks 320, 322 and 324, in higher performance circuits. Various enhancements are made to achieve system improvements. For example, back-to-back latches of the same phase 302 and 304, or a latch 306 which is updated on a specific conditional signal (for example, a condition signal from combinational logic block B 324 which is AND gated with an phase clock signal using AND gate 310) are implemented to reduce the number of circuit elements in a system, thereby reducing the size of the system 300. A multiple-phase clock system 300 is timed using a multiple-phase clocking scheme, which is depicted in a timing diagram shown in FIG. 4A and FIG. 4B.
Unfortunately the multiphase functionality of such complex systems typically does not allow simulation or emulation on a single-clock-edge based tool. In multiple-phase circuit operation, certain elements are updated only on particular phase clock edges. However, in a single-clock-edge based tool all sequential elements must be updated during each clock cycle. Furthermore, conditional updating of latches, which is extremely useful in a multiple-phase design, is not supported in a single-clock-edge based system because such updating violates the requirement that all sequential elements are updated on every designated transition of a clock edge.